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Patent Searching and Data


Title:
EXECUTING TIME INSTRUCTION OPTIMIZING SYSTEM
Document Type and Number:
Japanese Patent JPH04329437
Kind Code:
A
Abstract:

PURPOSE: To execute an executing program at high speed by optimizing and vectorizing it in the case of execution.

CONSTITUTION: When there is no in-cache instruction 4 to be executed in an instruction cache 3, an instruction executing means 2 activated by a program executing request 1 activates a cache load means 7 and when there is the in- cache instruction, the in-cache instruction 4 held in the instruction cache 3 is executed. The cache load means 7 inputs the plural instructions for an executing program 9 held in a main storage device 8 and outputs them as the in-cache instructions 4 to the instruction cache 3, and a scolar instruction optimizing means 5 and an instruction vectorizing means 6 are activated. The scolar instruction optimizing means 5 optimumly replaces the in-cache instruction 4 held in the instruction cache 3. The instruction vectorizing means 6 replaces the in-cache instruction 4 held in the instruction cache 3 with the vectorized in-cache instruction 4.


Inventors:
MATSUO SHIGEYA
Application Number:
JP12863191A
Publication Date:
November 18, 1992
Filing Date:
April 30, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F9/38; G06F12/08; G06F17/16; (IPC1-7): G06F9/38; G06F15/347
Attorney, Agent or Firm:
Kawahara Junichi