To provide an exposure mask along with the manufacturing method of a semiconductor device capable of suppressing shortening as well as defective connection of a wiring or shortening in a lithography process in manufacturing a semiconductor device.

A mask pattern 10 for an exposure mask consists of a wiring pattern 11 which ultraviolet light penetrates, and an auxiliary pattern 12 which is formed inside the wiring pattern 11 to shield the ultraviolet light. The auxiliary pattern 12 is formed in a second region 11-2 other than a first region 11-1 at the end 11a of the wiring pattern 11 parallel to the lengthwise direction of the wiring pattern 11 while away from the side surface of the wiring pattern 11. The length of the auxiliary pattern 12 in widthwise direction is set to be such value as not focused on a focusing plane where a mask pattern is focused. In the focusing plane, the illuminance of the region corresponding to the first region 11-1 of the wiring pattern 11 increases relative to the region corresponding to the second region 11-2, enlarges the region of uniform exposure amount, and suppresses shortening.