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Patent Searching and Data


Title:
FABRICATION OF DOUBLE LAYER GATE PROGRAM ROM
Document Type and Number:
Japanese Patent JPH0697395
Kind Code:
A
Abstract:

PURPOSE: To shorten turnaround time by performing ion implantation on condition that first and second gate layers are penetrated but the overlapped part thereof is not penetrated thereby retarding shift of mask.

CONSTITUTION: P-type ions are implanted from above first and second poly-Si layers 9, 10 using a mask M based on a data program. In this regard, acceleration voltage of ion implantation is set such that the ions pass through the parts only of the first and second poly-Si 9, 10 but do not pass through the overlap 11 of the first and second poly-Si 9, 10. Consequently, the part 11A below the overlapped part 11 is left in depletion type. Furthermore, mask of ion implanting region is self-aligned with a channel region through the overlapped part.


Inventors:
IWASE TAIRA
Application Number:
JP24681992A
Publication Date:
April 08, 1994
Filing Date:
September 16, 1992
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C17/12; H01L21/8246; H01L21/8247; H01L27/112; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; G11C17/12; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Kazuo Sato (3 others)