Title:
FABRICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2713232
Kind Code:
B2
Abstract:
PURPOSE: To prevent leakage owing to cracking of insulating film beneath a bonding pad in a short time by forming a diffusion layer, having conductivity type opposite to that of a substrate, beneath the bonding pad simultaneously with a depletion transistor.
CONSTITUTION: After forming a transistor region, a field oxide 2b, a diffusion layer 5a for preventing reversal, a gate electrode 7, a source-drain diffusion layer 5c and an interlayer insulation film 6 on a substrate 1, photoresist is applied and then it is removed from the channel region of a depletion transistor and from beneath a pad. Subsequently, impurity ions having conductivity type opposite to that of the substrate 1 are implanted at an energy required for transmitting through the gate electrode 7 or the field oxide 2b and the interlayer insulation film 6. With such method, a diffusion layer of opposite conductivity type can be formed beneath a pad simultaneously with a depletion transistor.
Inventors:
Masahiro Kobayashi
Toshimi Miju
Toshimi Miju
Application Number:
JP13617195A
Publication Date:
February 16, 1998
Filing Date:
May 10, 1995
Export Citation:
Assignee:
NEC
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Domestic Patent References:
| JP6466963A | ||||
| JP4333248A | ||||
| JP3280441A | ||||
| JP63166273A | ||||
| JP59210667A | ||||
| JP5228265A | ||||
| JP49115276A | ||||
| JP57166039A | ||||
| JP61131856U |
Attorney, Agent or Firm:
Soro Koro
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