Title:
FADING SIMULATOR
Document Type and Number:
Japanese Patent JP3854974
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform the simulation of a propagation environment by a three-dimensional model with less operation quantity and increase the number of paths which can be reproduced at one time.
SOLUTION: An FIFO type memory 301 is prepared by a maximum path number N, and delays an input signal by a delay quantity controlled by a DSP 303. A complex multiplier 302 is prepared by the maximum path number N, and multiplies the input signal delayed by the memory 301 by a complex coefficient controlled by the DSP 303. The DSP 303 sets the delay quantity of the memory 301 corresponding to a parameter of the delay time, and sets a complex coefficient of the complex multiplier 302 on the basis of a parameter of reception power and a phase parameter. A compositor 304 composites the output signal of the complex multipliers 302.
More Like This:
Inventors:
Takayuki Toyama
Ikuo Hiradate
Tetsuro Imai
Shinichi Ichitsubo
Ikuo Hiradate
Tetsuro Imai
Shinichi Ichitsubo
Application Number:
JP2004113578A
Publication Date:
December 06, 2006
Filing Date:
April 07, 2004
Export Citation:
Assignee:
Panasonic Mobile Communications Co., Ltd.
NTT DoCoMo, Inc.
NTT DoCoMo, Inc.
International Classes:
G01R29/08; G01R29/10; H04B7/26; H04B17/00; H04B17/391; H04W16/22; H04W16/28; H04W24/00; H04W24/06; H04W92/10; (IPC1-7): H04B17/00; G01R29/10; H04B7/26
Domestic Patent References:
| JP11145917A | ||||
| JP2003283442A | ||||
| JP2001160789A |
Attorney, Agent or Firm:
Koichi Washida
Previous Patent: METHOD AND APPARATUS FOR COLLECTING BLOOD FOR DIAGNOSTIC TEST
Next Patent: FADING SIMULATOR
Next Patent: FADING SIMULATOR