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Patent Searching and Data


Title:
FALSE CONTOUR CORRECTING CIRCUIT
Document Type and Number:
Japanese Patent JPH0662280
Kind Code:
A
Abstract:

PURPOSE: To perform false contour correction reducing picture quality degradation by generating a correcting output which has no regularity in the manner of an image.

CONSTITUTION: This circuit is provided with a random number generator 13 to generate a digital random number (x). A low-order bit (e) of an inputted digital video signal (a) and the digital random number (x) of the random number generator 13 are inputted to a discrimination circuit 11. The discrimination circuit 11 discriminates the levels of the input signals and applies a correcting output (y) of '1' or '0' to an adder 12. The adder 12 adds the correcting output to a high-order bit (f) of the video signal and generates a correcting signal (d). Therefore, the correction of the low-order bit (e) is performed in the manner of probability corresponding to the high-order bit (f) of the digital video signal (a). Thus, the picture quality can be prevented from being lowered by performing the false contour correction which has no regularity in the manner of the image.


Inventors:
MORITA HISAO
Application Number:
JP23307692A
Publication Date:
March 04, 1994
Filing Date:
August 06, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04N5/208; H04N9/68; (IPC1-7): H04N5/208; H04N9/68
Attorney, Agent or Firm:
Yoshiki Okamoto