PURPOSE: To surely execute the evaluation of all parity check circuits by inverting a parity bit value outputted from a register corresponding to the parity check circuit concerned out of plural parity check circuits at the time of deciding the generation of a false fault detected by the parity check circuit itself.

CONSTITUTION: It is defined that the code numbers of parity error detecting circuits 26, 27 are respectively '1' and '2', the circuit 26 always detect a parity error and the circuit 27 is allowed to detect a parity error only when a specific condition is satisfied. The polarity of the parity bits of parity errors 22, 23 respectively corresponding to the circuits 26, 27 is respectively intermittently or fixedly inverted by exclusive OR circuits 24, 25 in accordance with a code number specified by a diagnostic processor 2. Consequently, the evaluation of all the parity error detecting circuits 26, 27 can surely be executed and time required for the evaluation can be shortened.