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Title:
FAULT DETECTING SYSTEM
Document Type and Number:
Japanese Patent JPS62232042
Kind Code:
A
Abstract:

PURPOSE: To heighten inspection the ability to the normality of information channel connecting a duplex device and a unitizing device by verifying information in two time slots for normality confirming signal in an operating system and a standby system.

CONSTITUTION: A duplex device 1a has an operating system duplex device 1b as the standby system, and normality confirming signal adding circuits 16a, 16b and normality confirming signal examining circuits 17a, 17b are provided in these duplex devices 1a, 1b respectively. Controlling information 14 from a controller in the unitizing device 2 is transferred to selection circuits 6a, 6b, and normality confirming signals (A) 9a, 9b and a normality confirming signal (B) 12 are inserted to it and transferred to duplex devices 1a, 1b as return paths 4a, 4b of an information channel. Time slots (A), (B) 18a, 18b for normality confirming signal in the return paths of information channel are inspected respectively by normality confirming signal examining circuits 17a, 17b in the duplex devices 1a, 1b.


Inventors:
YAGI HISAO
Application Number:
JP7427686A
Publication Date:
October 12, 1987
Filing Date:
April 02, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/16; H04M3/22; (IPC1-7): G06F11/16; H04M3/22
Attorney, Agent or Firm:
Masaki Yamakawa



 
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