PURPOSE: To improve the reliability of a system by reading EPROM data successively and calculating vertical parity values when a CPU does not access an EPROM, and comparing them with a set value and generating a fault detection signal.

CONSTITUTION: Buffers 2 and 3, and 4 and 5 are provided to separate access from the CPU1 to the EPROM6, and a gate 8 which inputs a clock CK to a terminal CK unless the access is attained is provided in front of a counter 9; and its outputs is supplied to a counter 10 and data is read out of the EPROM through the buffer 5 successively and supplied to a parity calculating circuit 11. A vertical parity value calculated by the circuit 11 is compared with the set value of a parity value setting circuit 13 by a comparator 14 to generate the fault detection signal by a flip-flop 15 unless they coincide with each other. Consequently, fault detection is possible while the CPU1 attains no access to the EPROM6.