PURPOSE: To attain higher integration without increasing a wiring area by making a storage capacity per memory cell multi-valued.

CONSTITUTION: Capacitor columns 1 are composed of n ferroelectric capacitors C1-Cn. Since residual polarization is positive or negative, binary information is stored in the capacitor and thus the respective capacitors have bits of binary information by means of the parallelly arranged structure. Consequently, n capacitors are utilized as a 2n multi-valued memory and the storage capacity per a capacitor is increased. By the parallel arrangement of capacitors, a set of outside wirings is required for a cell and the wiring area is not increased. An inverted voltage required for polarizing inversion of each capacitor is made to be different and writing is started from a capacitor of maximum inversion potential successively to a capacitor of smaller inversion potential. Contrary to writing, reading is successively performed from the capacitor of minimum inversion potential to the capacitor of maximum inversion potential.