Title:
強誘電トランジスター、および、そのメモリーセル構造における使用方法
Document Type and Number:
Japanese Patent JP3977079
Kind Code:
B2
Abstract:
A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.
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Inventors:
Stengle, Reinhard
Reisinger, Hans
Honeyed, thomas
Bach hoffer, halald
Reisinger, Hans
Honeyed, thomas
Bach hoffer, halald
Application Number:
JP2001527365A
Publication Date:
September 19, 2007
Filing Date:
September 29, 2000
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
H01L21/8246; H01L21/8247; H01L27/105; H01L29/51; H01L29/78; H01L29/788; H01L29/792
Domestic Patent References:
| JP6504409A | ||||
| JP8264665A | ||||
| JP10135362A | ||||
| JP5121758A | ||||
| JP5121759A | ||||
| JP5121760A | ||||
| JP5121761A | ||||
| JP5121762A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko