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Patent Searching and Data


Title:
FET GATE BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPS5564407
Kind Code:
A
Abstract:

PURPOSE: To make it possible to supply the best gate bias to an apparatus with a high-frequency circuit by reversely biasing between the gate and source of FET on the basis of the output of a rectifying method of rectifying the output of a sine wave generating method.

CONSTITUTION: High frequency (RF) input (f0) is applied to mixing method 1 through input capacitor C0. Local oscillating stage 2 consists of transistor Q0, etc., applied with the output of tank circuit 3, and the emitter output of transistor Q0 is positively fed back by way of a electrostatic capacity divider circuit composed of capacitors C5 and C6 so as to extract sine-wave output (fosc). Further, rectifier circuit 4 consists of capacitor C10 holding the peak value of diode D0. Mixing stage 1 consists of a tuning circuit composed of common-source N-channel depletion MOSFETM0, capacitor C8 and coil L0. To gate G of FETM0, output-V of rectifier circuit 4 is applied by way of resistance R7.


Inventors:
MANABE KOUTAROU
Application Number:
JP13787678A
Publication Date:
May 15, 1980
Filing Date:
November 10, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03D7/12; (IPC1-7): H03F1/30
Domestic Patent References:
JPS4727562A