Title:
FET TYPE OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP3194506
Kind Code:
B2
Abstract:
PURPOSE: To form the output circuit which can set plural output levels and is provided with wide compatibility without changing an LSI or the circuit.
CONSTITUTION: An acceleration circuit C2 is provided with a selector circuit C3 and corresponding to the combination of potentials to be applied to select signal input terminals S1 and S2, the selector circuit C3 is operated and selects one of three states of an always valid state, always invalid state and temporary valid state of the acceleration circuit C2. Thus, the same circuit can provide plural interface operations.
Inventors:
Masafumi Nogawa
Yuusuke Otomo
Yuusuke Otomo
Application Number:
JP27564193A
Publication Date:
July 30, 2001
Filing Date:
November 04, 1993
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H03K17/687; H03K19/0175; H03K19/0185; (IPC1-7): H03K19/0185
Attorney, Agent or Firm:
Masataka Kobayashi