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Title:
FIELD EFFECT TRANSISTOR HAVING CHANNEL PART OF SUPERLATTICE CONSTRUCTION
Document Type and Number:
Japanese Patent JPS6127681
Kind Code:
A
Abstract:

PURPOSE: To obtain a stable and high-speed operable field effect transistor by employing a superlattice construction formed by laminating semiconductor thin films of two kinds of semiconductors having different forbidden bands alternately in channel parts.

CONSTITUTION: A hetero junction superlattice construction formed by laminating very thin films of two kinds of semiconductors having different forbidden bands alternately is employed in channel parts. The said hetero junction superlattice construction is formed by alternately laminating super thin layers of crystals Si and Si1-xGex, non-crystalline Si and Si1-xNx, non-crystalline Si and Si1-xCx or the like. For example, a non-crystalline a-Si1-xNx:H layer 7 containing hydrogen and a non-crystalline a-Si:H layer 8 are alternately laminated on a semiconductor bulk layer 1. With the thickness of each layer W selected in the range of 30∼200, an active layer 2 of a heterojunction superlattice construction of which channels are formed during operation is rovided and a source electrode 3, a drain elecerode 4, a gate electrode 5 and a gate insulating film 6 of SiO2, Si3N4 or the like are provided too, thereby to produce a thin film field effect transistor.


Inventors:
HIROSE ZENKO
MIYAZAKI SEIICHI
Application Number:
JP14795784A
Publication Date:
February 07, 1986
Filing Date:
July 17, 1984
Export Citation:
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Assignee:
JAPAN RES DEV CORP
International Classes:
H01L29/812; H01L21/20; H01L21/338; H01L29/10; H01L29/201; H01L29/778; H01L29/78; H01L29/786; (IPC1-7): H01L29/201; H01L29/80
Domestic Patent References:
JPS5984475A1984-05-16
JP55500196Y
JPS55117281A1980-09-09
JPS53131779A1978-11-16
Attorney, Agent or Firm:
Fumihiro Hasegawa