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Patent Searching and Data


Title:
FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS5814576
Kind Code:
A
Abstract:

PURPOSE: To improve voltage withstanding capabilibities by elevating the voltage triggering an avalanche multiplication phenomenon along a boundary layer by a method wherein the contact length between a depletion layer and a buffer layer is made larger for the purpose of maintaining low the electric field intensity along the boundary between the active layer and the buffer layer.

CONSTITUTION: A GaAs buffer layer 2 is stacked on a GaAs substrate 1, then is covered with an N type GaAS active layer 3'. The central part of the surface of an active layer 3' is provided with a gate electrode 4 on the both sides of which a source electrode 5 and a drain electrode 6 are formed flanking the electrode 4. The thickness of the active layer 3' is not uniform, thicker at the drain side and growing gradually thinner toward the source side. The length of the depletion layer 7, generated below the gate electrode, with which said layer 7 contacts the buffer layer 2, or the length l of the effective buffer part 8', becomes longer, resulting in a voltage drop reducing the voltage applied to the boundary between the layers 3' and 2. In consequently, the layer 2 is provided with higher withstanding capabilities and will be broken down only when higher drain voltages are applied thereto.


Inventors:
KODAMA KUNIHIKO
Application Number:
JP11180281A
Publication Date:
January 27, 1983
Filing Date:
July 17, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/80; H01L21/338; H01L29/08; H01L29/10; H01L29/812; (IPC1-7): H01L29/80
Attorney, Agent or Firm:
Kugoro Tamamushi