PURPOSE: To speed up the read operation of a file memory by controlling the output of the file memory always in an enable condition in an allowable range.

CONSTITUTION: An address outputted from an address chip select generating circuit 3 is automatically increased at the rear edge (rise) of an address decode signal 15 and the read of a file memory 4 of the next address can be executed without waiting for the access signal of a CPU 1. There, the file memory 4 is always set in a read condition except at the time of setting the access address of the file memory 4, at the time of the read of a status register 7 and the time of the write of the file memory 4. Thus, the read operation of the file memory 4 can be speeded up.