Title:
FILTER AND CARRIER PHASE ESTIMATING DEVICE USING THE SAME
Document Type and Number:
Japanese Patent JP3179267
Kind Code:
B2
Abstract:
PURPOSE: To obtain a carrier phase estimating device 10 which a satisfactory bit error ratio characteristic can be realized by satisfactorily following a carrier phase fluctuating by phasing.
CONSTITUTION: A reception IF signal 3 is converted into digital base band signals In and Qn by a base band conversion circuit 1. Those signals In and Qn are non-linearly converted into signals In' and Qn' by a non-linear circuit 12, and those signals In' and Qn' are respectively inputted to filters 24 and 25. The inputted signal In' is held by each stage of a shift register 15 in each prescribed timing. A signal from each stage of the shift register 15 is multiplied by a weighting factor (ck) by a multiplier 26 provided corresponding to each stage, added by an adder 16, and divided by the number N of the stages of the shift register by a divider 17. That is, the weighted mean value of each signal In' is calculated, and an estimated carrier phase Θn is calculated by a coordinate conversion circuit 18.
Inventors:
Nobuhisa Kataoka
Application Number:
JP30258293A
Publication Date:
June 25, 2001
Filing Date:
December 02, 1993
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H04L27/22; H04L27/18; H04L27/233; H04L27/00; (IPC1-7): H04L27/22
Other References:
石川博康 小林英雄「二重差動符号化によるＭＰＳＫ遅延検波用周波数オフセット補償方式」、１９９２年電子情報通信学会秋季大会講演論文集、第２−２５１頁、論文番号 Ｂ−２４８。
Attorney, Agent or Firm:
Toshihiko Kanayama (2 outside)