Title:
FILTER CIRCUIT
Document Type and Number:
Japanese Patent JP3429426
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent deterioration in the arithmetic accuracy due to residual charges in the filter circuit using an analog arithmetic circuit.
SOLUTION: An input analog signal is sequentially sampled and held by each of sample-and-hold circuits H1-H16, multiplied with a coefficient stored in a shift register SR at multipliers M1-M16 and the results are added by an adder circuit ADD. Accumulation of transfer errors of sample data is prevented by shifting coefficients stored in the shift register SR. Each of the sample-and- hold circuits H1-H16 and each of the multipliers M1-M16 are made up of an analog arithmetic circuit and incorporated with a switch to eliminate residual charges. A sample-and-hold circuit HS and a multiplier MS are used to substitute the functions of the sample-and-hold circuits H1-H16 and the multipliers M1-M16 and in this case, the sample-and-hold circuits H1-H16 and the multipliers M1-M16 are refreshed sequentially. The adder circuits ADD are provided in duplicate and refreshed similarly.
Inventors:
Kotobuki Guoliang
Qin Akira
Motonashi Kazunori
Makoto Yamamoto
Nao Takatori
Qin Akira
Motonashi Kazunori
Makoto Yamamoto
Nao Takatori
Application Number:
JP7921397A
Publication Date:
July 22, 2003
Filing Date:
March 14, 1997
Export Citation:
Assignee:
Takayama Co., Ltd.
International Classes:
H03H15/02; H03H17/02; H03H19/00; (IPC1-7): H03H15/02
Domestic Patent References:
| JP6164320A | ||||
| JP8327675A | ||||
| JP637686B1 |
Attorney, Agent or Firm:
Hideo Takahashi (1 person outside)