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Patent Searching and Data


Title:
FILTER CIRCUIT
Document Type and Number:
Japanese Patent JPH11163681
Kind Code:
A
Abstract:

To prevent the harmful effects of a multiplexer to the reference voltage by setting a period when a sample hold circuit output is cut from the reference voltage in a switching mode of them by means of the multiplexer which alternatively outputs the input voltage or the reference voltage.

A multiplexer MUX30 consists of a pair of CMOS switches T51 and T52 which are connected to the input voltage Vin5 and the reference voltage Vref respectively. A control signal is generated from a pre-control signal Pct, and the signal Pct is inputted to a buffer circuit consisting of buffers B51 and B52 and turned into a delayed pre-control signal Pct'. In a period covering the rise through the fall of an inverted OR ct1, both control signals are set at low levels to prevent the overlapping between the output of Vin5 and the output of Vref. In other words, the output of the MUX30 is kept stable and gives no harmful effect to the Vref even when a multiplier is circularly switched at a high speed.


Inventors:
SUZUKI KUNIHIKO
SHU NAGAAKI
Application Number:
JP34376297A
Publication Date:
June 18, 1999
Filing Date:
November 28, 1997
Export Citation:
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Assignee:
YOZAN INC
International Classes:
H03H19/00; H03H17/02; (IPC1-7): H03H19/00; H03H17/02
Attorney, Agent or Firm:
Yamamoto Makoto