PURPOSE: To reduce the capacity of a buffer register, by reading the filter coefficient in plural times into the buffer register within a single unit operation time and then applying the filter coefficient to a characteristic variable switched capacitor filter.

CONSTITUTION: The data on the filter coefficient which is stored in an ROM3 is read out in accordance with the address given from a clock generating circuit 2. This data is read temporarily and in plural times into the buffer registers 5-1 and 5-2 of 8 bits as well as 5-3 and 5-4 of 8 bits respectively within a single unit operation time which is decided by the sampling frequency. Then the filter coefficient is read out by the clock pulse given from the circuit 2 and applied to the characteristic variable switched capacitor filters 1 and 1'. In such way, the capacity of the buffer register can be reduced.