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Patent Searching and Data


Title:
FINISHING METHOD FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2000349216
Kind Code:
A
Abstract:

To provide a finishing method for an integrated circuit of high manufacture yield, small number of maintenance processes, lower cost of tool and spare parts, etc., high manufacture precision, less labor in inspection and check of an integrated circuit after manufacture, and low manufacturing cost.

Burring of resin, removing of tie bars and pinches, and cutting of leads are performed with a plurality of integrated circuits 1 formed on a lead frame 2, and the integrated circuits 1 are separated each other. Here, with a laser protective mask 3, which allows transmission of laser beam only at the work part of the lead frame 2 provided, laser working/cutting is performed on the work part of the lead frame 2 through the laser protective mask 3.


Inventors:
TANIYAMA MITSUHARU
Application Number:
JP15823799A
Publication Date:
December 15, 2000
Filing Date:
June 04, 1999
Export Citation:
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Assignee:
SONY CORP
International Classes:
B23K26/38; B23K26/066; H01L23/50; B23K101/40; (IPC1-7): H01L23/50; B23K26/00; B23K26/06