PURPOSE: To write two or more data arrays in one serial/parallel conversion type FIFO (first in first out) memory by transferring a flag bit indicating whether a data is the final data of a series of data array or not, the number of significant bits of data and one-word parallel data synchronously.

CONSTITUTION: An input counter 2 counts up the number of input bits of a converting circuit 3, and when the number of bits of one word width reaches (n), the flag, the number of significant bits and one-word parallel data are written in a flag register 5, a count register 6 and a stack memory 7, respectively. When an input enable signal E is still "1", "0", the number of significant bits (n) and the parallel data are written in said resisters and memory respectively. When the data reaches the rightmost end of the memory 7, an output controlling circuit 8 detects said state, stores the contents of the register 5 and also stores the contents of the register 6 in the counter 9. At that time, an empty signal EMP is turned to "0" and the contents of the memory 7 which are stored in a converting circuit 10 are shifted out in series by the number of significant bits. When the counter 9 is turned to "0", the control circuit 8 takes out the succeeding data from the memory 7 if the holding flag is "0".