Title:
【発明の名称】コンデンサ電極とMOSトランジスタのソース/ドレイン領域との間に接触を製造するための方法
Document Type and Number:
Japanese Patent JP3233935
Kind Code:
B2
Abstract:
PCT No. PCT/DE93/00078 Sec. 371 Date Aug. 4, 1994 Sec. 102(e) Date Aug. 4, 1994 PCT Filed Feb. 1, 1993 PCT Pub. No. WO93/16490 PCT Pub. Date Aug. 19, 1993.To make a contact between a capacitor electrode (13) disposed in a trench (11) and an MOS transistor source/drain region disposed outside the trench, a shallow etching is carried out in a self-aligned manner with respect to a field-oxide region insulating the MOS transistor by producing the trench (11) in a substrate (1). After forming an Si3N4 spacer (10) at the edge (8), laid bare during the etching, of the substrate (1) the part laid bare of the field-oxide region (2) is first removed with the aid of a mask and the trench (11) is completed in a further etching. The contact is produced after the formation of an SiO2 layer (12) at the surface of the trench (11) after removing the Si3N4 spacer (10) and producing the capacitor electrode (13) at the edge (8), laid bare by removing the Si3N4 spacer (10), of the substrate (1).
Inventors:
Racener, Wolfgang
Hoffman, Franz
Richie, Rotal
Hoffman, Franz
Richie, Rotal
Application Number:
JP51356193A
Publication Date:
December 04, 2001
Filing Date:
February 01, 1993
Export Citation:
Assignee:
Siemens Aktiengesellschaft
International Classes:
H01L21/82; H01L21/8242; H01L27/10; H01L21/76; H01L27/108; (IPC1-7): H01L27/108; H01L21/76; H01L21/8242
Domestic Patent References:
| JP2301164A | ||||
| JP2260655A | ||||
| JP2103961A | ||||
| JP2234466A | ||||
| JP2249266A | ||||
| JP4252071A | ||||
| JP4212451A |
Attorney, Agent or Firm:
Iwao Yamaguchi