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Title:
FLATTENING METHOD OF SHALLOW ISOLATION TRENCH
Document Type and Number:
Japanese Patent JP3245076
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To flatten a TEOS SiO2-filled isolation trench without chemical and mechanical polishing by transferring a flat face on structure to a TEOS SiO2 layer by etching having low selectivity and etching a section up to the top face of an Si3N4 passivation layer by a specific TEOS SiO2/Si3N4 high selective substance.
SOLUTION: A flattening medium 24 is formed onto structure 10, and a flat face obtained is transferred onto a TEOS SiO2 (TSO) layer 2 by dry etching having low selectivity. The structure 10 is dry-etched by a TSO/Si3N4 high selective chemical substance etching TSO at at least octuple speed faster than Si3N4, and etching is stopped when etching reaches the top face of an Si3N4 passivation layer 12. Accordingly, TSO-filled shallow isolation trenches in the semiconductor structure 10 coated with the Si3N4 passivation layer 12 parting shallow trenches filled with a TSO conformal layer 22 formed to an upper section in a silicon substrate 11 is flattened.


Inventors:
Philip Coronel
Frederick Leblanc
Renzo McCanan
Application Number:
JP29849496A
Publication Date:
January 07, 2002
Filing Date:
November 11, 1996
Export Citation:
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Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/302; H01L21/3065; H01L21/76; H01L21/822; H01L21/8242; H01L27/04; H01L27/108; (IPC1-7): H01L21/3065; H01L21/76; H01L21/822; H01L21/8242; H01L27/04; H01L27/108
Domestic Patent References:
JP5206261A
JP6112192A
JP4370934A
JP786239A
JP62274082A
JP574737A
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)



 
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