Title:
FLAW EVALUATION DEVICE
Document Type and Number:
Japanese Patent JP2009145114
Kind Code:
A
Abstract:
To provide a flaw evaluation device accurately detecting a flaw position of a semiconductor device.
The flaw evaluation device 101 is equipped with: a stage 6 which mounts the semiconductor device 21 and is made revolvable so as to incline the semiconductor device 21, a photographing part 7 for photographing the semiconductor device 21; and a flaw position detection part 5 for detecting the flaw position of the semiconductor device 21 on the basis of the light emitted from the semiconductor device 21 or the current generated in the semiconductor device 21. The optical axis of the photographing part 7 passes the center of revolution of the stage 6.
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Inventors:
MIZUKI TOSHIO
Application Number:
JP2007320887A
Publication Date:
July 02, 2009
Filing Date:
December 12, 2007
Export Citation:
Assignee:
SHARP KK
International Classes:
G01N27/00
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
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