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Patent Searching and Data


Title:
FLIP CHIP PACKAGE TEXTURE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2006295127
Kind Code:
A
Abstract:

To provide an FC package structure that prevents the reliability from lowering for substrate reflow and reduces the cost, maintaining the yield of a product and its manufacturing method.

This package manufacturing method provides a substrate 60 with multiple IC substrate units 60a each of which has a connection pad 62 on the surface. It forms an insulated layer 64 having a pattern, covering the substrate 60 and the connection pad 62 and additionally forms a hole which partially exposes the upper surface of each connection pad 62, filling the hole with a conductor material 68 to provide multiple chips 70 whose multiple conductive bumps 72 are established on the lower surfaces. In addition, each chip 70 is adhered to the surface of an IC substrate unit 60a and then the substrate 60 is cut off, so that multiple FC package structures can be produced, each having at least one chip 70 on the surface.


Inventors:
HSU SHIH-PING
Application Number:
JP2006020179A
Publication Date:
October 26, 2006
Filing Date:
January 30, 2006
Export Citation:
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Assignee:
PHOENIX PREC TECHNOLOGY CORP
International Classes:
H01L23/12; H01L21/60
Attorney, Agent or Firm:
Seishiro Suzuki