To prevent a decreased operating speed due to clock skew, resulting from an inverter gate delay and to reduce the number of circuit components by eliminating the need for an inverter that generates a select signal and an inverse of a clock signal for the flip-flop circuit with selector.

A 1st input data signal A is connected to a source of a P- channel MOS transistor(TR) P01, a 2nd input data signal B is connected to a source of an N-channel MOS TR N01, gates of both the TRs are connected in common, to which a select signal S is inputted and drains of both the TRs are connected in common to a flip-flop circuit section. Thus, an inverse to the select signal and an inverter to generate this signal are not required, malfunctions due to clock skew resulting from a gate delay are eliminated at high speed operation is avoided, a frequency margin is improved, and also the circuit scale is reduced. Even at the flip-flop circuit section, a transistor gate section is configured by a single MOS transfer gate for obtaining a similar effect.