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Patent Searching and Data


Title:
FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JP2008054275
Kind Code:
A
Abstract:

To solve a problem that electric power for a clock signal charging/discharging inside a flip-flop circuit is relatively large.

The flip-flop circuit 300 is provided with a master latch circuit 310 which latches input data according to the clock signal. A first input inverter 401 in the master latch circuit 310 inverts the input data. A second input inverter 402 inverts output data from the first input inverter 401. The first input inverter 401 is provided with a first and second push-pull transistors M31, M32 which receive input from a prestage in parallel, and a first control transistor M33 which controls conductive/non-conductive state between a first node Na and a predetermined fixed potential. The second input inverter 402 has the same structure.


Inventors:
SEKINE SATORU
FURUICHI SHINJI
Application Number:
JP2007020166A
Publication Date:
March 06, 2008
Filing Date:
January 30, 2007
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H03K3/3562; H03K3/037
Attorney, Agent or Firm:
Sakaki Morishita