Title:
FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JP3513376
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a CMOS flip-flop circuit which is operated at low power consumption.
SOLUTION: This flip-flop circuit consists of a master latch 100 and a slave latch 101. A data read circuit 102 sets a state of a node 1, based on a data input signal D when a clock input signal is at a first level. A data latch circuit 100 fixes a state of the node 1, when the signal CK is at a second level. A signal changeover circuit 104 latches a state of a node 2 to be a prescribed state, when the signal SCK is at the first level and sets a state of the node 2 based on the state off the node 1 when the signal CK is at the second level. A data read circuit 105 sets a state of the node 3 based on the state of the node 2, when the signal CK is at the second level. Then a data latch circuit 106 latches a state of the node 3, when the signal CK is at the first level.
Inventors:
Sato, Yuichi
Application Number:
JP31791297A
Publication Date:
March 31, 2004
Filing Date:
November 19, 1997
Export Citation:
Assignee:
SHARP CORP
International Classes:
H03K3/037; H03K3/3562; (IPC1-7): H03K3/037; H03K3/3562
Attorney, Agent or Firm:
佐野 静夫
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