PURPOSE: To prevent an external output from having a hazard by ORing a clock input with a set or reset input connected to the input of a gate, and generating an internal clock.

CONSTITUTION: The clock input CK and reset input R are connected to the inputs of an NOR gate G5. NOR Gates G1 and G2 and a switching gate A2 constitute a master flip-flop MF and NOR gates G3 and G4 and a switching gate A4 constitutes a master/slave flip-flops SF. A switching gate A1 is provided between a data input D and the master flip-flop MF, and a switching gate A3 is provided between the master flip-flop MF and a slave flip-flop SF. Information applied to the data input D is read at a rise of the clock input CK and transmitted to an output Q at a fall of the clock CK; when the set input S is 1, the output Q is 1 and when the reset input R is 1, the output Q is 0. When the reset input S is 0 and the reset input R and data input D are both 1 in this circuit, the internal clock C is invariably 1 even when the clock input CK varies, so none of switching gates A1∼A4 performs switching operation and a hazard, therefore, occurs to neither output Q.