Title:
FLOATING PINT SUM OF PRODUCTS ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JPS63244268
Kind Code:
A
Abstract:
PURPOSE:To speed up arithmetic operation and to reduce the quantity of hardwares by decreasing software operation necessary for one-time sum of products arithmetic operation. CONSTITUTION:From the multiplier side, together with the exponent value 106 of an uncorrected product and a mantissa value 108, an exponent correction value 110 is transmitted to the adder-side, and when the exponent value of a sum is calculated, the correction of the exponent value of the product also is executed. In this case of aligning digits prior to the adding of the mantissa values, the correction of the mantissa value of the product also is executed. Accordingly, an exponent correction value 125 as well as the exponent value 114 of the uncorrected sum and a mantissa value 125 is outputted, and the correction is executed at the time of the following adding in the operation of sum of products similarly as in the case of correcting a product. As a result, comparing with conventional floating point sum of products arithmetic unit, one-time operation of sum of products does not necessitate two times of shifting action, and, two shift circuits are eliminated, hence the speedup of processing and the reduction of the quantity of hardwares are attained.
Inventors:
MAENOBU KIYOSHI
Application Number:
JP7770287A
Publication Date:
October 11, 1988
Filing Date:
March 31, 1987
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/10; (IPC1-7): G06F15/31
Attorney, Agent or Firm:
Akira Kobiji (2 outside)
Previous Patent: WINDOW TRANSACTION PROCESSING SYSTEM
Next Patent: VECTOR ARITHMETIC PROCESSOR WITH MASK
Next Patent: VECTOR ARITHMETIC PROCESSOR WITH MASK