PURPOSE: To provide a floating point adder-subtracter for executing the addition and subtraction of floating point numbers at a high speed by the circuit constitution of a smaller scale.

CONSTITUTION: This floating point adder-subtracter is mainly constituted of a mantissa adder 112, the complementer 114 of '1' and a mantissa incrementing device 117. It is noticed that the rounding and turning to an absolute value of a mantissa part in the addition and subtraction of the floating point numbers are exclusively generated in the following two cases. In the case of true addition or true subtraction for which an exponent difference is not '0', mantissa addition and subtraction is executed in the mantissa aader 112 and then the rounding is accurately performed by the mantissa incrementing device 117. In the case of the true subtraction for which the exponent difference is '0' the mantissa adder 112 calculates a mantissa difference and when the mantissa difference is a negative number, the absolute value of the mantissa is obtained by the complementer of '2' constituted by combining the complementer 114 '1' and the mantissa incrementing device 117. Since only one mantissa adder is required, the circuit scale is drastically reduced compared to a conventional one.