PURPOSE: To execute an instruction which requires the reading of an operand except for a general-purpose register at the same speed as the execution of an instruction which does not require the reading of an operand except for the general-purpose register to improve performance by executing a floating- point operation in parallel with the reading of the operand.

CONSTITUTION: An instruction reader 1, an instruction decoding device 2, an arithmetic unit 3, an operand write device 4, an input/output bus 5 and a bus controller 6 are provided. When the instruction decoding means 2 decodes the instruction of an integer system or a floating-point system which requires the reading of the operand except for the succeeding general-purpose register while the floating-point operation concerning the instruction of the floating-point operation system is executed, the reading of the operand except for the general- purpose register is instructed and the reading of the operand is executed in parallel. Thus, the execution of the instruction which requires the reading of the operand except for the general-purpose register can be realized at the same speed as that of the instruction which does not require the reading of the operand except for the general-purpose register without providing an independent pipe line stage which pre-reads the operand, and performance can be improved.