Title:
FLOATING POINT MULTIPLIER
Document Type and Number:
Japanese Patent JP3492638
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accelerate the operation speed of a floating point multiplier.
SOLUTION: A multiplication array 11 inputs the mantissa parts M0 and M1 of m [bits] and outputs the partial products A and B of 2m-1. A mantissa part adder 12 and a post-rounding normalization judgment circuit 16 input the high-order m+1 [bits] of A and the high-order m [bits] of B and respectively output mantissa part added results C0 and C1 (=C0+1), carry X and a post- rounding normalization signal G. A sticky generation circuit 14 and a carry generation circuit 15 input the lower-order m-2 [bits] of A and the low-order m-1 [bits] of B and respectively output carry F and a sticky bit S. A rounding digit matching circuit 17 outputs the multiplied result H of this floating point multiplier from the output D0 and D1 of an exponent part adder 13 and the output C0 and C1 of the mantissa part adder 12 with the sticky bit S, the post- rounding normalization signal G and the carry X as control signals.
Inventors:
Takashi Nagata
Application Number:
JP2001048522A
Publication Date:
February 03, 2004
Filing Date:
February 23, 2001
Export Citation:
Assignee:
NC Computer Techno Co., Ltd.
International Classes:
G06F7/487; G06F7/507; G06F7/52; (IPC1-7): G06F7/52
Domestic Patent References:
| JP5150948A | ||||
| JP8185312A |
Attorney, Agent or Firm:
Masahiko Desk (2 outside)