Title:
FOCUS SERVO CIRCUIT
Document Type and Number:
Japanese Patent JP3678509
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform stable bias setting even if interferences such as damage or fingerprints occur by making a setting threshold value small when there is a focus error.
SOLUTION: A differential signal generating circuit 30 produces, based on an output from an optical pickup 20, a focus error signal and sends this signal to an adder 40. A driving circuit 50 receives a differential signal, a focus bias from a focus bias voltage generating circuit 70 being added thereto, and drives the focus actuator of the optical pickup 20. A jitter detecting circuit 60 outputs as a jitter quantity a phase difference between the edge of a reference clock synchronized with an EFM signal and the changing point of the EFM signal. A focus bias voltage adjusting circuit 100 swings the bias positive and negative and calculates an optimal bias for making jitter smallest based on a corresponding jitter quantity. Herein, if errors such as focus drop are detected during execution of optimization, setting is changed such that the determination threshold value of the jitter quantity is gradually reduced.
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Inventors:
Akira Inoue
Hiroshi Shiiki
Hiroshi Shiiki
Application Number:
JP25224896A
Publication Date:
August 03, 2005
Filing Date:
September 04, 1996
Export Citation:
Assignee:
Clarion Co., Ltd.
International Classes:
G11B7/085; G11B7/09; (IPC1-7): G11B7/09; G11B7/085
Domestic Patent References:
| JP6231477A |
Attorney, Agent or Firm:
Teruo Aoki