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Title:
FORMATION OF METALLIC WIRING OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH10294294
Kind Code:
A
Abstract:

To bury a metallic wiring layer also in a contact hole of a large aspect ratio readily by forming a barrier metal layer all over an insulation film wherein a contact hole is incorporated and forming a high density plasma CVD metallic wiring layer on the barrier metal layer.

After a photosensitive film PR is applied all over a second insulation film 29, the photosensitive film PR is patterned to expose the second insulation film 29 of a contact hole formation region. The second insulation film 29 and a first insulation film 28 are removed by etching by using the patterned photosensitive film PR as a mask and a contact hole 30 which exposes one surface of a semiconductor substrate wherein a source/drain region 26 is formed. A barrier metal layer 31 is formed in a surface of the second insulation film 29 including a surface of a semiconductor substrate inside the contact hole 30. A metallic wiring layer 32 is formed to completely fill up the contact hole 30 by high density plasma vapor growth method all over the barrier metal layer 31.


Inventors:
LEE CHANG JAE
PARK NAE HAK
Application Number:
JP9579098A
Publication Date:
November 04, 1998
Filing Date:
April 08, 1998
Export Citation:
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Assignee:
LG SEMICON CO LTD
International Classes:
H01L21/285; H01L21/205; H01L21/28; H01L21/336; H01L21/768; H01L29/78; (IPC1-7): H01L21/285; H01L21/205; H01L21/336; H01L21/768; H01L29/78
Attorney, Agent or Firm:
Masaki Yamakawa