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Title:
FORMATION METHOD FOR INTERLAYER INSULATION FILM OF SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JP2000036498
Kind Code:
A
Abstract:

To provide the formation method of an interlayer insulation film, especially for shortening chemical mechanical polishing process time in the manufacturing method of a semiconductor element.

This formation method for the interlayer insulation film of the semiconductor element is provided with the stage of forming a first insulation film 50 on a semiconductor substrate provided with an element such as a transistor in the inside, the stage of forming many metal wirings 60 made of the laminated structure of a Ti/TiN film 52, an Al film 54 and a TiN film 56 on the first insulation film, the stage of forming a spacer 70a made of the TiN film on the side face of the metal wirings, a stage of forming many metal wirings provided with the spacer and a second insulation film 72 formed of an insulation material, whose vapor deposition speed is made different by the material of a lower film on the first insulation film, the stage of forming a third insulation film 74 on the second insulation film and the stage of polishing the third insulation film by a CMP(chemical-mechanical polishing) process.


Inventors:
KIN CHOKEI
CHO YURAI
Application Number:
JP16812599A
Publication Date:
February 02, 2000
Filing Date:
June 15, 1999
Export Citation:
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Assignee:
TOBU DENSHI KK
International Classes:
H01L21/3205; H01L21/31; H01L21/768; H01L23/52; H01L23/522; H01L21/316; (IPC1-7): H01L21/3205; H01L21/28; H01L21/768
Attorney, Agent or Firm:
Shuichiro Kitamura