Title:
FORMATION OF VIA HOLE
Document Type and Number:
Japanese Patent JPH04137751
Kind Code:
A
Abstract:
PURPOSE: To form an accurate via hole by performing plasma etching through a photoresist pattern, provided on the silicon nitride layer of a double-layer dielectric forming the silicon nitride layer on a silicon oxide layer. CONSTITUTION: In order to form a via on the double dielectric, composed of an SiO layer 18 formed on integrated circuit substrates 12 and 14 and an SiN layer 20 formed on it, a photoresist layer 22 is formed on the SiN layer 20, and subsequently the resist pattern of a via hole 10 is formed. Then, the SiN and SiO layers are etched through the via hole on the resist layer, and the via hole is formed on the double-layer dielectric. For the etching of the SiN layer, plasma for selectively etching SiN is used rather than the SiO layer. After the SiN layer has been etched, the via hole is extended through the SiO layer to the upper surface of a metal wire by selective plasma etching to metal, and a metallization layer is deposited on the dielectric, while including the inside of the via hole. Thus, formation for the via hole can be improved.
Inventors:
BARERII EE BATSUHA
Application Number:
JP41675090A
Publication Date:
May 12, 1992
Filing Date:
December 28, 1990
Export Citation:
Assignee:
HEWLETT PACKARD CO
International Classes:
H01L21/302; C04B41/53; C04B41/91; H01L21/3065; H01L21/311; H01L21/768; H01L23/522; (IPC1-7): H01L21/302; H01L21/90
Attorney, Agent or Firm:
Kimihisa Kato