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Title:
FORMING METHOD OF CONDUCTIVE PATTERN
Document Type and Number:
Japanese Patent JPH09260293
Kind Code:
A
Abstract:

To enable a semiconductor layer of low resistance to be formed only on a specific base material by a method wherein a P-type or an N-type conductive pattern is selectively formed on a patterned ground material provided onto a base by a hot CVD method where germanium halide and silane are used as a raw material.

Germanium halide and silane are used as a raw material, including dopant gas such as diborane, phosphine, arsine or the like, and it is preferable that a P-type or an N-type SiGe of low resistance is selectively formed on a patterned conductive ground material provided onto a base material by a hot CVD method at a temperature of 500°C or below by the use of the above raw material. It is important that germanium halide such as germanium fluoride or germanium chloride and silane, disilane, or halogen derivatives of them effective for the reduction of germanium halide are used as material gas for selectively depositing a P-type or an N-type SiGe of low resistance on a patterned ground material. In this case, material gas can be diluted with inert gas or hydrogen.


Inventors:
HANNA JUNICHI
Application Number:
JP10878496A
Publication Date:
October 03, 1997
Filing Date:
March 25, 1996
Export Citation:
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Assignee:
HANNA JUNICHI
International Classes:
C23C16/04; H01L21/205; H01L21/28; H01L21/285; H01L21/3205; (IPC1-7): H01L21/205; C23C16/04; H01L21/28; H01L21/285; H01L21/3205