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Title:
FORMING METHOD FOR GATE ELECTRODE OR WIRING
Document Type and Number:
Japanese Patent JPH04142777
Kind Code:
A
Abstract:

PURPOSE: To prevent an undercut from occurring in a gate electrode, the corner of a polycrystalline silicon from protruding in an after oxidation process, and a channel section from being affected in impurity concentration by a method wherein a patterned polycrystalline silicon is thermally treated to enable impurities to diffuse from an impurity diffusion source, and a polycrystalline silicon film is set low in resistance.

CONSTITUTION: A phosphorus glass layer 4 serving as an impurity source of phosphorus is formed on the upside of a polycrystalline silicon film 3. Thereafter, an oven is heated up to a temperature of 850-900°C (phosphorus starts diffusing into silicon) in five minutes or so, kept at this temperature for five minutes, and then returned to a normal temperature in five minutes or so, and a substrate 1 is taken out of the oven. Therefore, in this state, phosphorus contained in the phosphorus glass layer 4 has been partially diffused into the polycrystalline silicon film 3, and an impurity concentration gradient is formed in the film 3 in such a manner that impurities become gradually smaller in concentration starting at the surface of the film 3 toward the inside. Only the polycrystalline silicon film 3 under a resist 5 is left unremoved, and the film 3 concerned is made to serve as a gate electrode G.


Inventors:
KATAYAMA SATOSHI
Application Number:
JP26602790A
Publication Date:
May 15, 1992
Filing Date:
October 03, 1990
Export Citation:
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Assignee:
KAWASAKI STEEL CO
International Classes:
H01L23/52; H01L21/28; H01L21/3205; H01L29/423; H01L29/43; H01L29/49; H01L29/78; (IPC1-7): H01L21/28; H01L21/3205; H01L29/62; H01L29/784
Attorney, Agent or Firm:
Tetsuya Mori (3 others)



 
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