Title:
FORMING METHOD FOR WIRING PATTERN
Document Type and Number:
Japanese Patent JPS57162331
Kind Code:
A
Abstract:
PURPOSE:To improve the wiring density of a wiring pattern by exposing with electron beam a resist of the part corresponding to the profile of the pattern by employing a positive resist for the electron beam resist and reducing the area of emitting the beam for forming the pattern. CONSTITUTION:A positive resist is coated on an aluminum layer 3 formed on a substrate, is then prebaked, an electron beam is emitted to the resist to develop the pattern, is then rinsed, and is then postbaked. With the pattern as a mask the aluminum layer 3 is etched by gas plasma to remove the resist, and an insulating layer 4 is exposed. Since the positive resist has good resolution for the electron beam and the stepped surface of the resist after the development is acute, fine region can be formed. Accordingly, many wires of the same thickness can be formed in the contact hall array of the lower layer at equal interval L between the contact hall arrays 7-11, 12-14.
Inventors:
YASUDA HIROSHI
BAN YASUTAKA
BAN YASUTAKA
Application Number:
JP4637181A
Publication Date:
October 06, 1982
Filing Date:
March 31, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/027; H01L21/30; H01L21/3213; H01L21/768; H01L23/528; (IPC1-7): H01L21/88
Domestic Patent References:
| JPS51147261A | 1976-12-17 |