PURPOSE: To reduce a minimum allowable phase difference, that is, a delay insertion/removal quantity by providing a frame conversion circuit applying high speed frame conversion in advance when a low speed input signal is overridden onto a high speed output signal.

CONSTITUTION: When an input signal DIN is overridden onto an output signal DOUT at the speed of four times that of the input signal, the input signal DIN is fed to a selective circuit 13 and a delay circuit 12 via a frame conversion circuit 16. A frame conversion circuit 16 applies frame conversion compressing a signal in n-bit of one frame to attain the bit arrangement of nearly 4 times of speed to that of the input signal. Thus, after the frame conversion, an elastic storing memory 14 validates once for 4 times to a readout clock RCLK and the compressed n-bit output signal WD is read from the elastic storing memory 14, then an output signal DOUT is obtained, in which the input signal is spread on the frame of the output signal RD of the elastic store memory 14, that is, the input signal DIN is packed from the head of the frame up to the n-th bit.