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Title:
FRAME ALIGNER
Document Type and Number:
Japanese Patent JPS63200639
Kind Code:
A
Abstract:

PURPOSE: To decide the output frame phase whose delay is minimized automatically by using a phase at first fed with an output clock pulse after the point of time written with an input signal to a FIFO memory as an output frame phase with respect to an optional input signal frame phase.

CONSTITUTION: In the first-in first-out (FIFO) memories 5-1∼5-N, when an input signal is written from the head of the input frame the moment the input frame phase is detected, the input frame phase is detected as the output frame phase in all the FIFO memories 5-1∼5-N. After the point of time when the input signal is written in the FIFO memories 5-1∼5-N, the phase fed at first with the output clock pulse is used as the reference. Moreover, when an idle memory is detected in the FIFO memories 5-1∼5-N, a read clock is stopped. Thus, the read phase with minimized delay is decided automatically.


Inventors:
OKUMURA YASUYUKI
HAYASHI KAZUHIRO
KAKINUMA TAKAMA
Application Number:
JP3234887A
Publication Date:
August 18, 1988
Filing Date:
February 17, 1987
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04J3/06; H04L7/00; (IPC1-7): H04J3/06; H04L7/00
Attorney, Agent or Firm:
Takashi Honma



 
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