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Patent Searching and Data


Title:
FRAME MEMORY WRITING CONTROL CIRCUIT AND ITS METHOD
Document Type and Number:
Japanese Patent JPH0876731
Kind Code:
A
Abstract:

PURPOSE: To greatly simplify a circuit for forming the perpendicular direction address of a frame memory necessary at the time of writing interlace signals into the frame memory.

CONSTITUTION: This frame memory writing control circuit has an H address forming circuit which forms and outputs the address in the horizontal direction of the frame memory in order to write the interlace signals thinned with a prescribed thinning rate into the frame memory and a V address forming circuit which forms and outputs the address in the vertical direction. The V address forming circuit has a ROM 3 in which an address table having the vertical direction address corresponding to the thinning rate is stored. The vertical direction address of the frame memory is formed and outputted by referencing to this address table.


Inventors:
KOIKE YOICHI
Application Number:
JP21376194A
Publication Date:
March 22, 1996
Filing Date:
September 07, 1994
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/00; G09G5/00; G09G5/391; (IPC1-7): G09G5/00; G06F12/00; G09G5/00
Domestic Patent References:
JPH05284422A1993-10-29
JPH0695654A1994-04-08
Attorney, Agent or Firm:
京本 直樹 (外2名)