Title:
FRAME SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP3461522
Kind Code:
B2
Abstract:
PURPOSE: To provide a frame signal processor which is contained in a demodulator used for a receiver of a radio communications system applying a TDMA and a digital modulation system and also contains a frame synchronizing correlation that can produce a frame series correlation signal, i.e., the original of a frame synchronizing signal even in an environment where the large frequency offset exists.
CONSTITUTION: A frame signal processor is provided with a differential vector generating part 102 which generates a differential vector from an orthogonal base band signal 101, a vector normalizing part 103, and a vector correlation part 104 which secires the vector correlation between a normalized differential vector series and the differential vector series of a frame synchronizing signal. Thus it is possible to acquire a correlation signal, i.e., the original of the frame synchronizing signal even in a large frequency offset environment by securing the series correlation between both differential vector series.
Inventors:
Akihiko Matsuoka
Kennori Kunieda
Yuri Yamamoto
Kimihide Bihozu
Hiroshi Ohnishi
Kennori Kunieda
Yuri Yamamoto
Kimihide Bihozu
Hiroshi Ohnishi
Application Number:
JP3764193A
Publication Date:
October 27, 2003
Filing Date:
February 26, 1993
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H04J3/06; H04L7/08; H04L27/22; (IPC1-7): H04L27/22; H04J3/06; H04L7/08
Domestic Patent References:
| JP4196936A | ||||
| JP4172040A | ||||
| JP4346532A | ||||
| JP537511A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)