Title:
FRAME SYNCHRONIZATION CIRCUIT
Document Type and Number:
Japanese Patent JP3318243
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce an erroneous synchronization when a synchronization point is deviated backward from a true synchronization point due to fading in the frame synchronization circuit where the correlation between orthogonal detection data and a unique word UW is taken in each frame and a timing (position) of a maximum value is used as the synchronization point.
SOLUTION: A synchronization point range setting device 22 sets a fluctuation allowable range of a synchronization point, uses a position of a maximum correlation value within the range as a 1st synchronization point candidate and uses a position of a maximum correlation value within a frame as a 2nd synchronization point candidate. Equalization processing in a UW period is conducted about the respective candidates and the candidate having a smaller equalization error is discriminated to be a true synchronization point. Furthermore, in the case that the 2nd synchronization point candidate deviated backward from the fluctuation range is discriminated to be the synchronization point, the fluctuation range is change into a range including the position to discriminate about a succeeding frame.
Inventors:
Kamata
Application Number:
JP28108797A
Publication Date:
August 26, 2002
Filing Date:
September 30, 1997
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
H03H21/00; H03H17/00; H04B7/005; H04J3/06; H04L7/08; (IPC1-7): H04L7/08; H04B7/005; H04J3/06
Domestic Patent References:
| JP918395A | ||||
| JP8149056A |
Attorney, Agent or Firm:
Manabu Otsuka