PURPOSE: To provide the frame synchronization circuit with less hardware scale in the frame synchronization circuit in which an optional frame pattern is set.

CONSTITUTION: The circuit consists of a memory 1 in which a frame synchronization circuit pattern data and a valid bit designation data are written, a comparator section 2 comparing a frame synchronizing signal with a memory output signal, a monitor section 3 monitoring the result of comparison of the comparator section 2, a frame counter section 4 generating a memory address, a timing generating section 5 outputting a control signal of each section and a frame synchronization protection section 6 protecting a specified number of frames.