To enhance asynchronous transfer mode ATM cell extraction performance in a wireless asynchronous transfer mode WATM or a radio environment with a high error rate by realizing a frame synchronization algorithm in the form of an application specific integrated circuit ASIC.

The system is provided with a 4-byte shift register 1 for received data, a counter 2 for bytes and bits on the basis of a received byte clock, a memory controller 3 that controls the memory based on the 1st-3rd count signals, a memory 4 that stores three sub frames under the control of the memory controller 3, a demultiplex processor 5 that receives an output (OP-CNT) of the counter 2 and an output of the memory 4, a buffer 6 that receives three headers demux-outputted from the processor 5, a pattern comparator section 7 that compares a header value H1 in the 4-byte shift register 1 with values of header values H12-H14 from the buffer 6 and increments a value of an adder 8 by one each when a 16-bit value is F628 (H) or a high-order 8-bit value is E8 (H), and a state machine 9 that is synchronized when the received sum reaches a prescribed number or over.