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Patent Searching and Data


Title:
FRAME SYNCHRONIZING DEVICE
Document Type and Number:
Japanese Patent JPS6272241
Kind Code:
A
Abstract:

PURPOSE: To decrease the synchronizing word even if noise exists in a transmission line by measuring the content of a shift register through which a transmission data passes and the intensity of correlation as the content of a synchronizing word generating circuit and using a digital integration circuit to compare the measured value a threshold value after the measured value is integrated in a digital integration circuit by one frame period.

CONSTITUTION: The content of a shift register 6 through which a transmission data having a synchronizing word passes is compared and counted with the content of a synchronizing word generating circuit 7 by an exclusive OR circuit 8 and a measuring circuit 9 at each bit, the measured value representing the intensity of the correlation between the synchronizing word and the content of the shift register 6 is sent from the circuit 9 and inputted to a digital integration circuit 15. The integration circuit 15 consists of an adder circuit 10, a buffer memory 11 and an attenuation circuit 12, the own output is fed back to the adder circuit 10 through the attenuation circuit 12 while being subject to 1 frame delay, and the output of the circuit 9 is compared with a threshold value of a threshold value generating circuit 13 at a comparator circuit 14. Thus, even when the noise in a transmission line is large, the reduction in the accuracy is prevented and the synchronization by a short synchronizing word is attained.


Inventors:
TOMOYASU KEISUKE
Application Number:
JP21376285A
Publication Date:
April 02, 1987
Filing Date:
September 25, 1985
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04J3/06; H04L7/08; (IPC1-7): H04L7/08
Attorney, Agent or Firm:
Masuo Oiwa