Title:
FRAME SYNCHRONIZING SIGNAL DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS63179683
Kind Code:
A
Abstract:
PURPOSE:To surely detect a frame synchronizing signal by adding or subtracting an offset value to/from a digital value representing a frame synchronizing signal digitized in the event of clamping in error. CONSTITUTION:A frame synchronizing signal detection circuit 8 supervises a prescribed bit of a digital signal obtained from A/D conversion of an analog video signal of positive synchronizing form to detect a synchronizing signal. Then an offset circuit 11 adds or subtracts an offset set to a level within an amplitude of the frame synchronizing signal to/from the digital signal when the detection circuit 8 does not detect the frame synchronizing signal. Moreover, a bit discrimination circuit 12 selects the circuit so that a prescribed bit of an output signal of the offset circuit 11 is inputted to the detection circuit 8 corresponding to the digital signal when no frame synchronizing signal is detected. Thus, even when the clamping is applied to an erroneous level, the frame synchronizing signal is detected surely.
Inventors:
KITAGAWA SHINICHIRO
ASANO YOSHIKAZU
OSANAWA KAZUO
ASANO YOSHIKAZU
OSANAWA KAZUO
Application Number:
JP1071887A
Publication Date:
July 23, 1988
Filing Date:
January 20, 1987
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H04N5/10; H04L7/08; H04N7/015; H04N19/00; H04N19/59; H04N19/85; (IPC1-7): H04L7/08; H04N5/10; H04N7/00; H04N7/13
Attorney, Agent or Firm:
Koji Yasutomi (1 person outside)
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